The continuing dramatic increases in semiconductor complexity and performance are driving a dramatic rise in the complexity of IC Package designs. The performance rise into the multi-gigabit range is driving the need for 3D power, signal and thermal integrity analysis.

By providing the highest performance, best ease of use and pinpoint accuracy, our solutions allow engineers to create designs optimized for power and signal integrity in the shortest possible time. Through seamless integration with all of the major CAD design flows, Optimal solutions help customers achieve the shortest and most efficient overall design cycle time.

Optimal’s technology is embedded in the Cadence Allegro Platform and certified in the TSMC Reference Flow.

Optimal’s PakSi-TM is a thermal-mechanical analysis solution that allows engineers to perform thermal modeling and analysis of effects such as thermal resistance and thermally induced stress. In addition it provides analysis of solder joint fatigue, package warpage, and other mechanical stresses

Optimal’s O-Wave is a full-wave 3D EM analysis solution that allows engineers to perform extremely accurate signal integrity analysis with extremely high performance, capacity and accuracy. This allows engineers to analyze larger structures with fast turnaround time. O-Wave is typically 2-3X faster than competitive solutions. O-Wave has the ability to create fully-coupled ground bounce and SSN models.


DESIGN TYPE > SiP

As the consumer electronics market drives the continuous need to reduce product size, weight, power, cost, and time-to-market, System-in-Package (SiP) has emerged as a new technology to address this growing need. SiP design and analysis is significantly more complex than designing single-chip packages, and requires a new generation of design and analysis solutions. In SiP design, the package is no longer just a connectivity element between an IC and a PCB, it becomes an integration fabric. To address this, co-design of both the ‘chip and package’ and the ‘package and PCB’ becomes essential to a SiP design and analysis methodology. Endlessly flexible, SiP design can incorporate complex combinations of wire-bond, flip-chip, stacked devices, embedded devices, package-on-package and package-in-package.

Optimal's SiP Analysis suites allow for the modeling of complex structures such as mixed flip chip and wirebond assemblies, die stacks with interposers and spacers, double-sided assemblies and highly perforated power planes. Integrated into the major SiP design flows and through industry standards, circuit simulator neutral, the suite comprises the following new products:

Optimal SiP GH SI, quasi-static signal integrity (SI) analysis suitable for gigahertz frequencies.

Optimal SiP GH SPI, quasi-static SI analysis for gigahertz frequencies combined with DC and AC power integrity (PI) analysis for a complete SSN solution.

Optimal SiP MGH SI, quasi-static and full-wave SI analysis suitable for DC to multi-gigahertz frequencies.

Optimal SiP MGH SPI, multi-gigahertz SI and PI analysis combined for a complete SSN solution.

Optimal SiP Thermal, a new SiP thermal modeling and analysis solution.

Optimal’s goal is to be a leader in 3D signal and power integrity for SiP design. We are adapting our tools to handle the new requirements for SiP, we are delivering a new set of co-design solutions, and we are working closely with our strategic partners to integrate with their new generation of SiP design solutions and methodologies.

The fact is that an end product is comprised of packaged silicon on PCB systems. With the rising complexity of each component (Chip, Package, PCB), it’s becoming increasingly important to deploy a more concurrent design and analysis methodology to enable the co-design and co-optimization of chip, package, and PCB as a complete system.

Optimal’s co-design solutions enable concurrent analysis of the ‘chip and package’ and ‘package and PCB’.

Chip-Package Co-design

In the area of chip and package co-design, Optimal has formed a number of partnerships with leaders in both on-chip analysis and with innovators in chip-package co-design. For example:

	Cadence VoltageStorm integration – as part of our strategic partnership with Cadence, VoltageStorm can directly import accurate package models from PakSi-E to enable concurrent analysis of the chip and package.
	TSMC Reference flow – as part of TSMC’s reference flow 5.0 and 6.0, Optimal and TSMC have jointly developed and certified a Chip-Package co-design methodology.
	Rio RioMagic integration – Rio Design Automation is delivering a new generation of Package-aware Chip design solution that allows IC designers to concurrently design, analyze and optimize the chip design together with the package design. Optimal and Rio have jointly developed an integration of Optimal’s 3D signal and power integrity solutions with Rio’s RioMagic solution.

Package-PCB Co-design

Optimal’s 3D signal and power integrity solutions allow design teams to analyze multiple IC packages together with the PCB system that they are integrated with. The Package-PCB co-design solution supports the reality that in many cases the PCB and IC Package are designed in different CAD systems.