Chips Don't Float in Space! (But They Are Often Designed In A Vacuum) - Electronic Design

The challenges mount for designers working feverishly on the latest chips destined for the iPod, Blackberry, RAZR, or the next hot network chip set. These unlikely superheroes have tackled power, density, signal integrity, and much more. What's often overlooked is the not-so-insignificant fact that chips don't float in space — they are assembled onto packages and increasingly onto systems-in-packages (SiPs). Click for more

Optimal Expands System-in-Package Analysis - EDN

San Jose-based IC package and PCB signal, power and thermal integrity analysis tool supplier Optimal Corp. said today it has added chip-package-PCB co-design support to its system-in-package (SiP) analysis software. Click for more

DESIGN TOOLS: SiP suite adds co-design capabilities - EE Times

Many tools support signal-integrity or power analysis for chips, packages or boards individually, but analyzing them all together is a challenge. Optimal Corp. this week will announce chip/package/pc board co-design support in the form of enhancements to its Optimal SiP Analysis Suite for system-in-package (SiP) design. Click for more

EDA Cafe View From the Top Audio Interview

with Optimal CEO, Dave DeMaria

Dave is an accomplished, successful executive with over 20 years of experience in the EDA industry. Most recently Dave was at Cadence for over 7 years in a variety of executive roles. Click here for audio interview

Facilitating System-in-Package (SiP) Design

In the latest move in the cost, density, and time-to-market battles, a number of wireless and consumer-focused IC and systems companies are turning to System-in-Package (SiP) design to gain a competitive advantage. Hemmed in, on the one hand, by the technical challenges of producing compact, high-performance, multi-function products and, on the other, by a fast-moving, competitive marketplace, they are scrambling to reduce every cent in product cost and every hour spent in design. Click for more

DesignCon Management Forum: Why is EDA Stagnating, or is it?

This panel debated the state of EDA in today's exacting and demanding design world-whether we are in a situation where the design tools themselves are a hindrance to next-stage chip, package, and PCB design, or vital technology to accomplish next-level design. Click for more

Press coverage:

Gigabit talk dominates DesignCon (again) - EDN

Disruptive events could change EDA landscape, panelists say - EE Times

Help Wanted - ES Level Evangelist to Drive EDA Growth - Electronic News

Optimizing for 10 Gb/sec Differential Signal Transmission

Design fixes that work at 'normal' board speeds can cause havoc in the 10 Gb/sec arena. Modifying the trace pair can adversely affect everything from impedance to eye diagrams.

As 10Gb/sec signaling becomes more prevalent in board design, assumptions about what affects high-speed signal transmission may no longer be true. Previously, in the sub 10Gb/sec design era, one of the key trade-offs was balancing the capability of solvers with the requirements of getting high-speed serial channels to work properly. With significant advancements in both the capacity and the usability of full-wave solvers, designers have more choices and greater flexibility for designing and analyzing interconnects. Here we will discuss how to effectively use the greater flexibility of solvers to gain more insight into the design and shorten design cycles. Click for more

EDA Vendors are Helping IC and Packaging Designers Work More Effectively Together - EDN

Traditionally, separate groups designed ICs and packages, but cost, time-to-market issues, and ever-growing package complexity—especially as SIPs (systems in packages), multichip modules, and stacked die become more common—are now forcing IC and package designers to work together more closely. Luckily, a few EDA players...are now making concerted efforts to develop tools to help IC designers and package designers collaborate more effectively. Click for more

What Is the Most Cost-Effective and Performance-Efficient Path to DFY? - Chip Design Magazine

First of all, what are we really talking about when we say, "design for yield?" DFY isn't new. The companies that specialize in the development, design, and manufacture of complex ICs have been struggling with all aspects of DFY since the advent of the IC industry. To me, the irony of DFY is that it has less to do with design than it does with planning. DFY is an act of balancing economics and performance through a combination of designing for the following: capitalization on a window of opportunity, application compatibility, technical performance, and low cost. Click for more

The Optimal Solution - EDA Cafe, EDA Weekly

The weekly editorials have covered several vendors in the power integrity field. Some have attacked the issue through power management and some though power grid design. Optimal offers products with complete signal integrity and power integrity design flow from IC to Package to PCB. The company was founded in 1995 by Dr. An-Yu Kuo. The company's PakSi-E product is a 3D quasi-static electromagnetic simulation tool for electronic packaging. It provides whole package RLGC parasitic extraction. Click for more

Packaging Rides the Z Axis into the Third Dimension - Electronic Design

The push for 3D packaging of semiconductor ICs directly results from market demands for smaller and lower-profile, lighter, and lower-cost packaged ICs that consume less power. With such market forces at play, package designers are feeling the strain to keep pace with their IC chip designer brethren. Click for more

Best Practices in High Speed Design - SOCcentral.com

There's a new design challenge, on par with signal integrity, that threatens to kill or limit today's IC, package and PCB designs - power integrity (PI). Designers working on projects that require higher speeds and denser designs, which also include more interfaces on components, will have to contend with serious decreases in voltage supplies. This could result in a decrease in absolute margins. Click for more

Extending Bandwidth into the Gigabit Range - Printed Circuit Design & Manufacture

Today's package designers face gigabit signaling rates running through packages that require alternatives to lumped element modeling. Unfortunately, tradeoffs between using W-element models and multisegment models are not always obvious. This article will discuss some of those tradeoffs and look at a specific example where we extend the bandwidth of an existing package model with a multisegment approach. Click for more

Power Integrity Comes Home To Roost At 90 nm - Electronic Design

IC designers know the litany backwards and forwards: Area, power, and speed are the primary tradeoffs when it comes to optimizing your designs. You can usually have two out of the three, but a design rarely manages to optimize all of them. Click for more

Special Market Focus: Collaborative Design - Electronic News

In the consumer electronics space, where products are embraced at breakneck speed, making it to market first can mean the difference between leading the pack, slugging it out later on pricing or -- worse -- being ignored completely. Design organizations are under pressure to get superior designs to market faster than the competition, to take full advantage of shrinking windows of opportunity for maximum ROI. Click for more

Power Tool Unites Package, PCB - EE Times

Printed-circuit-board designers are having severe problems with IC packages that don't work once they're placed on a board. Optimal Corp. this week will offer a solution with PowerGrid, a power integrity analysis tool aimed at designers of both IC packages and pc boards. Click for more

If they come, Can you build it? - Electronic News

Electronic News sat down to discuss design for manufacturability and whether the concept works with Len Perham, CEO of Optimal; Vincent Tong, VP of product technology for Xilinx’s advanced products group; Walter Ng, senior director of design solutions at Chartered Semiconductor; and Graham Bell, senior director of marketing at Nassda. What follows are excerpts of that conversation. Click for more

Chip-Package Co-design: Capabilities Improving, Need Growing - Semiconductor International

The last few editions of the International Technology Roadmap for Semiconductors (ITRS) have called for the development and improvement of chip-package-board codesign capabilities. Faster, more complex chips with ever-increasing numbers of I/Os and power connections drive this need, as well as the increasing number of systems-in-package (SiPs). Some surprising cost factors are also driving codesign. Click for more

Riding the 'wave' of 90nm signal integrity - EE Design

We've all talked, and even groused, about the difficulty of moving from 130nm to 90nm. As designers of electronic components — chips, packages or PCBs — that go into an electronic end product, we all know that current tools, methodologies and processes simply can't keep up with the manufacturing processes. Click for more

Signal integrity needs to be unified across the board at 90nm - EDN

At 90nm, IC designers must account for an entirely new range of electrical effects they previously could have safely bypassed. Paying attention to the full range of electrical effects is not a choice once designs go to 90 nm...it’s an imperative. Click for more

Full-wave analysis tools target 2 GHz+ - EE Times

EDA signal integrity startup Optimal Corp. has released a series of tools for 3-D full-wave signal integrity simulation, analysis and verification for high-speed IC, package and pc-board designs. Click for more

Using S-parameters for signal integrity analysis - EE Design

The signal integrity analysis of high-speed electronic designs requires that the interconnect models be valid over a wide bandwidth. To represent the frequency-dependent behavior of a complex structure, S parameters, which have long been used in the microwave community, are beginning to gain popularity in the analog and digital designs. Click for more

Speedy FPGAs need IC/package co-design - EE Times

Until recently, chip designers mainly focused on optimizing their designs within the silicon. But as clock frequencies started moving into the gigahertz range, the designers found that the package could become one of the elements that limited the performance of an IC. This new focus played a role for us at Xilinx, when we designed our next-generation, multiprocessor FPGA platform family and products. Click for more

Cadence teams with startup for packaging solution - EE Design

Claiming to offer the industry's first integrated IC packaging design and signal-integrity analysis solution, Cadence Design Systems on Wednesday (Oct. 1) announced Advanced Packaging Engineer 3D (APE-3D), which includes a 3D field solver from startup Optimal Corp. The resulting solution, according to both companies, is both faster and more accurate than existing packaging tools. Click for more

EDA start up rides 'full wave' of signal integrity - EE Times

Claiming a technology breakthrough with its full-wave 3D extraction technology, Optimal Corp. is gearing up to provide a suite of signal-integrity analysis solutions for chips, packages and pc-boards. Click for more

Signal integrity start up appoints directors  - EE Times

Optimal Corp., a provider of signal integrity tools for ICs, pc-boards, and packages, has appointed two electronics industry veterans to its board of directors. Optimal selected Len Perham as chairman and Frank Lee as a new board member. Click for more